IBM and partners Sony/Toshiba, unveil Cell processor

The chip was shown for the first time at the International Solid State Circuits Conference in San Francisco. The processor uses Rambus's XDR memory and FlexIO processor bus interface (formerly known as Redwood). These allow the Cell's speed to be taken advantage of with fast transfer between the Cell and its memory and i/o.

The Cell has a modular design based on a slightly less powerful I.B.M. processor that is currently in G5 64-bit desktop computers from Apple Computer. Additionally, the Cell architecture is distinguished by the fact that it controls an array of eight additional processors that the design team refers to as synergistic processing elements, or S.P.E.'s. Each of the S.P.E.'s is a 128-bit processor in its own right.

The Cell has some components that in the lab switch at 5.6 GHz, and several people familiar with the design said that it was both more flexible than is generally understood and that it has been designed with high bandwidth communications, such as high-speed data links to homes, in mind.

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